1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor integrated circuit (IC) including an additional pad for reducing the number of pads receiving a test address and thereby increasing the number of semiconductor ICs that can be tested simultaneously during a wafer test process, and a method of testing a wafer including a semiconductor IC.
2. Description of the Related Art
Semiconductor IC chips are formed on wafers during a semiconductor manufacturing process. Wafer-level testing is generally performed to eliminate defective IC chips before they are packaged, thereby reducing the cost of packaging and package-level testing of chips that are already known to be defective. In a wafer test process, only certain properties of the semiconductor IC chips are tested rather than testing all properties of the chips. For example, activation of memory cells on a semiconductor IC chip may be the only property that is tested at the wafer level.
Wafer testing is performed using test addresses generated by applying voltages to pads of a semiconductor IC chip. The voltages are generated by a driver on an external test device connected to a probe card. The test voltages may be used during a wafer testing process to determine, for example, whether a memory cell corresponding to a test address is activated.
Generally, multiple semiconductor IC chips are tested simultaneously, and the number of semiconductor IC chips that can be tested simultaneously is determined by the number of pins on the probe card and the number of drivers on the external test device. In other words, the number of semiconductor IC chips that can be tested simultaneously is determined by the number of test channels that can electrically connect chip pads to the test device.
However, as the integration level of semiconductor IC chips increases, the number of address bits (the number of pads) also increases. As a result, the number of semiconductor IC chips that can be tested simultaneously decreases since the number of test channels is limited even though the required number of address bits increases. Therefore, the productivity of the semiconductor IC chip manufacturing process decreases.